Levantamiento de los deterioros de los portales de la calle Joaquín de Agüero en la ciudad de Ciego de Ávila, Cuba

Ciego de Avila city shows an urban image regular, rectangular.Thishas been, since the foundation of the city until today, and its distinctive feature is a system of wide public arcades. For that reason, it is known"The Portal´s City". This city has a large group of eclectic constructions with high patrimonial values. The work of the Patrimony Office has been directed at the conservation of aconstructions complex, which are part of its cultural patrimony, where some areas have been deteriorated considerably. Therefore, the objective of this work is to carry out the survey of deterioration, which has been caused, by wear, and time, in the structural and decorative elements of Joaquín de Agüero Street, in the limits of the historic center, in order to know, what kind, and different degree of damage occurs in the constructions.La ciudad deCiego de Ávila se destaca por una imagen urbana regular en su trazado ortogonal, conformado por manzanas rectangulares y cuadradas, retícula esta que se ha respetado desde la formación de la ciudad hasta la actualidad; su característica más significativa es los amplios corredores públicos,por eso es considerada “La Ciudad de los Portales”, donde atesora un numeroso grupo de construcciones eclécticas con un alto valor patrimonial.El trabajo de la oficina de patrimonio ha estado encaminado a la conservación de las diferentes construcciones patrimoniales de la cuidad que presentan cierto grado de deterioro por diversas causas. El objetivo de este trabajo está encaminado a la realización de una caracterización de los daños y deterioros presentes en los elementos estructurales y decorativos de la calle Joaquín de Agüero en los límites del centro histórico con la finalidad de conocer los disímiles daños que presentan las construcciones

A High-Efficiency Isolated Wide Voltage Range DC-DC Converter Using WBG Devices

The recent release of the standard USB-PD 3.1 speci es variable output voltages from 5 V to 48 V featuring a step forward towards a universal adaptor but rising new challenges for the converter topologies used up to now. In such applications, a rst AC-DC stage is followed by a DC-DC stage. In this paper, emerging WBG technologies are applied to the asymmetrical half-bridge yback topology, demonstrating the potential of such combination as a wide voltage range DC-DC stage. Its suitability for high-density and high-ef ciency USB-PD Extended Power Range (EPR) and battery charger applications is discussed. The impact of different switching technologies, silicon and wide band gap, is analyzed. A general method to dimension the converter is presented and an iterative process is used to evaluate the theoretical ef ciency under different conditions and switching devices. Finally, the advantages of the presented converter using Gallium Nitride (GaN) devices are demonstrated in a 240 W DC-DC prototype. It achieves a full load ef ciency of 98%, and it is able to deliver an output voltage from 5 V to 48 V with input voltage range from 120 V to 420 V, as well an outstanding power density of 112 W/inch3 uncased.Infineon Technologies AG through the Spanish Regional Project P20_00265 BRNM-680-UGR20Spanish Ministry of Science MCIN/AEI PID2020-117344RB-I0

Highly Reliable Quadruple-Node Upset-Tolerant D-Latch

This work was supported in part by the Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00, and in part by the Regional Government under Grant P20_00265 and Grant P20_00633.As CMOS technology scaling pushes towards the reduction of the length of transistors, electronic circuits face numerous reliability issues, and in particular nodes of D-latches at nano-scale confront multiple-node upset errors due to their operation in harsh radiative environments. In this manuscript, a new high reliable D-latch which can tolerate quadruple-node upsets is presented. The design is based on a low-cost single event double-upset tolerant (LSEDUT) cell and a clock-gating triple-level soft-error interceptive module (CG-SIM). Due to its LSEDUT base, it can tolerate two upsets, but the combination of two LSEDUTs and the triple-level CG-SIM provides the proposed D-latch with remarkable quadruple-node upsets (QNU) tolerance. Applying LSEDUTs for designing a QNU-tolerant D-latch improves considerably its features; in particular, this approach enhances its reliability against process variations, such as threshold voltage and (W/L) transistor variability, compared to previous QNU-tolerant D-latches and double-node-upset tolerant latches. Furthermore, the proposed D-latch not only tolerates QNUs, but it also features a clear advantage in comparison with the previous clock gating-based quadruple-node-upset-tolerant (QNUTL-CG) D-latch: it can mask single event transients. Speci c gures of merit endorse the gains introduced by the new design: compared with the QNUTL-CG D-latch, the improvements of the maximum standard deviations of the gate delay, induced by threshold voltage and (W/L) transistors variability of the proposed D-latch, are 13.8% and 5.7%, respectively. Also, the proposed D-latch has 23% lesser maximum standard deviation in power consumption, resulting from threshold voltage variability, when compared to the QNUTL-CG D-latch.Spanish MCIN/AEI /10.13039/501100011033/ FEDER under Grant PID2020-117344RB-I00Regional Government under Grant P20_00265 and Grant P20_0063

Low-Cost Soft Error Robust Hardened D-Latch for CMOS Technology Circuit

In this paper, a Soft Error Hardened D-latch with improved performance is proposed, also featuring Single Event Upset (SEU) and Single Event Transient (SET) immunity. This novel D-latch can tolerate particles as charge injection in different internal nodes, as well as the input and output nodes. The performance of the new circuit has been assessed through different key parameters, such as power consumption, delay, Power-Delay Product (PDP) at various frequencies, voltage, temperature, and process variations. A set of simulations has been set up to benchmark the new proposed D-latch in comparison to previous D-latches, such as the Static D-latch, TPDICE-based D-latch, LSEH-1 and DICE D-latches. A comparison between these simulations proves that the proposed D-latch not only has a better immunity, but also features lower power consumption, delay, PDP, and area footprint. Moreover, the impact of temperature and process variations, such as aspect ratio (W/L) and threshold voltage transistor variability, on the proposed D-latch with regard to previous D-latches is investigated. Specifically, the delay and PDP of the proposed D-latch improves by 60.3% and 3.67%, respectively, when compared to the reference Static D-latch. Furthermore, the standard deviation of the threshold voltage transistor variability impact on the delay improved by 3.2%, while its impact on the power consumption improves by 9.1%. Finally, it is shown that the standard deviation of the (W/L) transistor variability on the power consumption is improved by 56.2%

Resonant Hybrid Flyback, a New Topology for High Density Power Adaptors

In this article, an innovative power adaptor based on the asymmetrical pulse width modulation (PWM) flyback topology will be presented. Its benefits compared to other state-of-the-art topologies, such as the active clamp flyback, are analyzed in detail. It will also describe the control methods to achieve high efficiency and power density using zero-voltage switching (ZVS) and zero-current switching (ZCS) techniques over the full range of the input voltage and the output load, providing comprehensive guidelines for the practical design. Finally, we demonstrate the convenience of the proposed design methods with a 65 W adaptor prototype achieving a peak efficiency of close to 95% and a minimum efficiency of 93.4% at full load over the range of the input voltage, as well as a world-class power density of 22 W/inch3 cased.This research is financed by Infineon Tecnologias AG

Rule-Based Design for Low-Cost Double-Node Upset Tolerant Self-Recoverable D-Latch

This paper presents a low-cost, self-recoverable, double-node upset tolerant latch aiming at nourishing the lack of these devices in the state of the art, especially featuring self-recoverability while maintaining a low-cost pro le. Thus, this D-latch may be useful for high reliability and high-performance safety-critical applications as it can detect and recover faults happening during holding time in harsh radiation environments. The proposed D-latch design is based on a low-cost single event double-node upset tolerant latch and a rule-based double-node upset (DNU) tolerant latch which provides it with the self-recoverability against DNU, but paired with a low transistor count and high performance. Simulation waveforms support the achievements and demonstrate that this new D-latch is fully self-recoverable against double-node upset. In addition, the minimum improvement of the delay-power-area product of the proposed rule-based design for the low-cost DNU tolerant self-recoverable latch (RB-LDNUR) is 59%, compared with the latest DNU self-recoverable latch on the literature.Spanish Government MCIN/AEI/10.13039/501100011033/FEDER PID2020-117344RB-I00Regional Government P20_00265 P20_00633 B-RNM-680-UGR2

Comparison of Laser-Synthetized Nanographene-Based Electrodes for Flexible Supercapacitors

In this paper, we present a comparative study of a cost-effective method for the mass fabrication of electrodes to be used in thin-film flexible supercapacitors. This technique is based on the laser-synthesis of graphene-based nanomaterials, specifically, laser-induced graphene and reduced graphene oxide. The synthesis of these materials was performed using two different lasers: a CO2 laser with an infrared wavelength of λ = 10.6 µm and a UV laser (λ = 405 nm). After the optimization of the parameters of both lasers for this purpose, the performance of these materials as bare electrodes for flexible supercapacitors was studied in a comparative way. The experiments showed that the electrodes synthetized with the low-cost UV laser compete well in terms of specific capacitance with those obtained with the CO2 laser, while the best performance is provided by the rGO electrodes fabricated with the CO2 laser. It has also been demonstrated that the degree of reduction achieved with the UV laser for the rGO patterns was not enough to provide a good interaction electrode-electrolyte. Finally, we proved that the specific capacitance achieved with the presented supercapacitors can be improved by modifying the in-planar structure, without compromising their performance, which, together with their compatibility with doping-techniques and surface treatments processes, shows the potential of this technology for the fabrication of future high-performance and inexpensive flexible supercapacitors.Spanish Ministry of Universities FPU16/01451University of Granada PPJIB2019-05Spanish Ministry of Science/FEDER-EU TEC2017-89955-PMexican Government through Conacyt A1-S-3553

Non-Linear Capacitance of Si SJ MOSFETs in Resonant Zero Voltage Switching Applications

The parasitic capacitances of modern Si SJ MOSFETs are characterized by their non-linearity. At high voltages the total stored energy Eoss(VDC) in the output capacitance Coss(v) differs substantially from the energy in an equivalent linear capacitor Coss(tr) storing the same amount of charge. That difference requires the de nition of an additional equivalent linear capacitor Coss(er) storing the same amount of energy at a speci c voltage. However, the parasitic capacitances of current SiC and GaN devices have a more linear distribution of charge along the voltage. Moreover, the equivalent Coss(tr) and Coss(er) of SiC and GaN devices are smaller than the ones of a Si device with a similar Rds;on. In this work, the impact of the nonlinear distribution of charge in the performance and the design of resonant ZVS converters is analyzed. A Si SJ device is compared to a SiC device of equivalent Coss(tr), and to a GaN device of equivalent Coss(er), in single device topologies and half-bridge based topologies, in full ZVS and in partial or full hard-switching. A prototype of 3300 W resonant LLC DCDC converter, with nominal 400 V input to 52 V output, was designed and built to demonstrate the validity of the analysis

Correlation between CD4 T cell counts and virus compartmentalization in genital and systemic compartments of HIV-infected females

AbstractThe majority of infection by the human immunodeficiency virus (HIV-1) across the world occurs by heterosexual transmission and is likely mediated by virus present in genital secretions. In spite of this, infection is followed by clinical markers of the virus present in blood, which may not be representative of the virus involved in transmission. In fact, several studies have demonstrated that the genital tract represents a unique compartment for the virus. We assessed the relationship between immune system integrity, represented by CD4+ T cell counts, and the maintenance of viral compartmentalization between plasma and vaginal fluid virus in treatment naïve women from the Dominican Republic infected by the heterosexual transmission route. We cloned and sequenced cell free virus from plasma and genital fluid samples from six women to assess viral evolution, phylogenetic relatedness, and calculated co-receptor use for the C2V3 region of the envelope. Our analyses demonstrated plasma and vaginal fluid virus compartments remained intact only in samples from women with CD4+ T cell counts over 350cells/μl. The majority of viral forms were predicted to use the CCR5 co-receptor, although several dual tropic forms were also identified. None of the clones were found to use the CXCR4 co-receptor even though many of the patients showed severe disease. Our findings lend further support to the role of an intact immune system in maintaining compartmentalization across blood and genital quasispecies and provide a compelling rationale to specifically consider genital tract viral forms in therapeutic and vaccine research

Temporal behavior and processing of the LiDAR signal in fog

The interest in LiDAR imaging systems has recently increased in outdoor ground-based applications related to computer vision, in fields like autonomous vehicles. However, for the complete settling of the technology, there are still obstacles related to outdoor performance, being its use in adverse weather conditions one of the most challenging. When working in bad weather, data shown in point clouds is unreliable and its temporal behavior is unknown. We have designed, constructed, and tested a scanning-pulsed LiDAR imaging system with outstanding characteristics related to optoelectronic modifications, in particular including digitization capabilities of each of the pulses. The system performance was tested in a macro-scale fog chamber and, using the collected data, two relevant phenomena were identified: the backscattering signal of light that first interacts with the media and false-positive points that appear due to the scattering properties of the media. Digitization of the complete signal can be used to develop algorithms to identify and get rid of them. Our contribution is related to the digitization, analysis, and characterization of the acquired signal when steering to a target under foggy conditions, as well as the proposal of different strategies to improve point clouds generated in these conditions.This work was supported by the Spanish Ministry of Science and Innovation (MICINN) under the project PID2020-119484RB-I00. The first author gratefully acknowledges the Universitat Politècnica de Catalunya and Banco Santander for the financial support of her predoctoral research grant.Peer ReviewedPostprint (author's final draft